<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="6.x">Drupal-Biblio</source-app><ref-type>10</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Chhokra, Ajay</style></author><author><style face="normal" font="default" size="100%">Abdelwahed, Sherif</style></author><author><style face="normal" font="default" size="100%">Dubey, Abhishek</style></author><author><style face="normal" font="default" size="100%">Neema, Sandeep</style></author><author><style face="normal" font="default" size="100%">Karsai, Gabor</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">From System Modeling to Formal Verification</style></title><secondary-title><style face="normal" font="default" size="100%">The 2015 Electronic System Level Synthesis Conference</style></secondary-title><tertiary-title><style face="normal" font="default" size="100%">ESLsyn2015</style></tertiary-title></titles><dates><year><style  face="normal" font="default" size="100%">2015</style></year><pub-dates><date><style  face="normal" font="default" size="100%">07/01/2015</style></date></pub-dates></dates><urls><related-urls><url><style face="normal" font="default" size="100%">https://archive.isis.vanderbilt.edu/sites/default/files/Session3_Paper3.pdf</style></url></related-urls></urls><publisher><style face="normal" font="default" size="100%">ECSI</style></publisher><pub-location><style face="normal" font="default" size="100%">San Francisco</style></pub-location><isbn><style face="normal" font="default" size="100%">979-10-92279-12-2</style></isbn><abstract><style face="normal" font="default" size="100%">Due to increasing design complexity, modern systems are modeled at a high level of abstraction. SystemC is widely accepted as a system level language for modeling complex embedded systems. Verification of these SystemC designs nullifies the chances of error propagation down to the hardware. Due to lack of formal semantics of SystemC, the verification of such designs is done mostly in an unsystematic manner. This paper provides a new modeling environment that enables the designer to simulate and formally verify the designs by generating SystemC code. The generated SystemC code is automatically translated to timed automata for formal analysis.</style></abstract></record></records></xml>